1. Field of the Invention
The present invention relates to a digital signal processing apparatus and a digital signal processing method, and particularly, to a digital signal processing apparatus and a digital signal processing method that perform digital signal processing in which the sampling frequency of an input signal differs from the sampling frequency of an output signal.
2. Description of Related Art
When the sampling frequency of an output signal is different from the sampling frequency of an input signal, it is necessary to use a digital signal processing apparatus such as a sampling rate converter that performs sampling rate conversion (SRC). In addition, a further digital signal processing apparatus for performing digital filtering will be required to perform digital filtering such as oversampling processing before and after SRC processing. One of the two digital signal processing apparatuses that are, namely, a sampling rate converter and a digital filter, operates in synchronization with the sampling frequency of the input signal. In other words, the apparatus operates in synchronization with an operation clock that is a fixed multiple of the sampling frequency of the input signal. In addition, the other digital signal processing apparatus operates in synchronization with the sampling frequency of the output signal. In other words, the apparatus operates in synchronization with an operation clock that is a fixed multiple of the sampling frequency of the output signal. Therefore, when the sampling frequency of the output signal is different from the sampling frequency of the input signal, it is necessary to use a plurality of digital signal processing apparatuses that operate in synchronization with different operation clocks. (For instance, refer to Japanese Patent Laid-Open No. H11-68727).
For example, when realizing interpolation processing in which the sampling frequency of the input signal digital data is 32 kHz and the sampling frequency of the output signal digital data is 48 kHz, a digital signal processing apparatus that performs interpolation processing on an operation clock synchronized to 32 kHz is first provided, and a digital signal processing apparatus that performs SRC processing with the interpolation result as input on an operation clock synchronized to 48 kHz is next provided.
As described above, digital signal processing in which the sampling frequencies of the input signal and the output signal differ requires two digital signal processing apparatuses that each operate in synchronization with the respective sampling frequencies. As a result, there is a problem in that the apparatus configuration required by digital signal processing increases, which in turn causes increases in circuit size, power consumption and the like.